View HYS64D32300HU-6-C_3191969.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

never stop thinking. hys[64/72]d64x20hu-[5/6]-c hys[64/72]d32x00hu-[5/6]-c hys64d16x01hu-[5/6]-c 184-pin unbuffered dual-in-line memory modules reg dimm ddr sdram data sheet, v1.0, july 2003 memory products
edition 2003-07 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys[64/72]d64x20hu-[5/6]-c hys[64/72]d32x00hu-[5/6]-c hys64d16x01hu-[5/6]-c 184-pin unbuffered dual-in-line memory modules reg dimm ddr sdram data sheet, v1.0, july 2003 memory products
template: mp_a4_v2.0_2003-06-06.fm hys[64/72]d64x20hu-[5/6]-c, hys[64/72]d32x00hu-[5/6]-c, hys64d16x01hu-[5/6]-c revision history: v1.0 2003-07 previous version: ? page subjects (major changes since last revision) all new data sheet template we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 current conditions and specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents
data sheet 6 v1.0, 2003-07 184-pin unbuffered dual-i n-line memory modules reg dimm hys[64/72]d64x20hu-[5/6]-c hys[64/72]d32x00hu-[5/6]-c hys64d16x01hu-[5/6]-c 1 overview 1.1 features 184-pin unbuffered dual-in-line memory modules (ecc and non-parity) for pc and server main memory applications one rank 16m x 64, 32m 64, 32m 72 and two ranks 64m 64, 64m 72 organization jedec standard double data rate synchronous drams (ddr sdram) single +2.5v ( 0.2v) power supply built with 256 mbit ddr sdram in p-tsopii-66-1 package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible serial presence detect with e 2 prom jedec standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. jedec standard reference layout gold plated contacts ddr400 speed grade supported lead-free 1.2 description the hys[64/72]d64x20hu-[5/6]-c, hys[64/72]d32x00hu-[5/6]-c, and hys64d16x01hu-[5/6]-c are industry standard 184-pin unbuffered dual-in-line memory modules (reg dimm) organized as 16m 64, 32m 64 and 64m 64 for non-parity and 32m 72 and 64m 72 for ecc main memory applications. the memory array is designed with 256mbit double data rate synchronous drams. a variety of decoupling capacitors are mounted on the printed circuit board. the dimms feature serial presence detect (spd) based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer table 1 performance part number speed code ? 5 ? 6unit module speed grade ddr400b ddr333b ? component module pc3200-3033 pc2700-2533 ? max. clock frequency @ cl = 3 f ck3 200 166 mhz @ cl = 2.5 f ck2.5 166 166 mhz @ cl = 2 f ck2 133 133 mhz
data sheet 7 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules overview note: all part numbers end with a place code designating the silicon-die revision. reference information available on request. example: hys72d32000hu-6-c, indicating rev. c dies are used for sdram components. the compliance code is printed on the module labels describing the speed sort (for example ?pc2700?), the latencies and spd code definition (for example ?20330? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jedec spd code definiton version 0), and the raw card used for this module. table 2 ordering information type compliance code description sdram technology pc3200 (cl=3) hys64d16301hu-5-c pc3200u-30330-c0 one rank 128mb dimm 256 mbit ( 16) hys64d32300hu-5-c pc3200u-30330-a0 one rank 256mb dimm 256 mbit ( 8) hys72d32300hu-5-c pc3200u-30330-a0 one rank 256mb ecc-dimm 256 mbit ( 8) hys64d64320hu-5-c pc3200u-30330-b0 two ranks 512mb dimm 256 mbit ( 8) hys72d64320hu-5-c pc3200u-30330-b0 two ranks 512mb ecc-dimm 256 mbit ( 8) pc2700 (cl=2.5) hys64d16301hu-6-c pc2700u-25330-c0 one rank 128mb dimm 256 mbit ( 16) HYS64D32300HU-6-C pc2700u-25330-a0 one rank 256mb dimm 256 mbit ( 8) hys72d32300hu-6-c pc2700u-25330-a0 one rank 256mb ecc-dimm 256 mbit ( 8) hys64d64320hu-6-c pc2700u-25330-b0 two ranks 512mb dimm 256 mbit ( 8) hys72d64320hu-6-c pc2700u-25330-b0 two ranks 512mb ecc-dimm 256 mbit ( 8) 1) rcd: row-column-delay
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration data sheet 8 v1.0, 2003-07 2 pin configuration note: s1 and cke1 are used on two rank modules only table 3 pin definitions and functions symbol type 1) 1) i: input; o: output; i/o: bidirectional in-/output; ai: analog input; pwr: power supply; gnd: signal ground; nc: not connected function a0 - a12 i address inputs ba0, ba1 i bank selects dq0 - dq63 i/o data input/output cb0 - cb7 i/o check bits ( 72 organization only) ras, cas , we i command inputs cke0 - cke1 i clock enable dqs0 - dqs8 i/o sdram low data strobes ck0 - ck2, i sdram clock (positive lines) ck0 - ck2 i sdram clock (negative lines) dm0 - dm8 dqs9 - dqs17 i i/o sdram low data mask/ high data strobes s0 , s1 i chip selects for rank0 and rank1 v dd pwr power (+2.5 v) v ss gnd ground v ddq pwr i/o driver power supply v ddid pwr vdd indentification flag v ref ai i/o reference supply v ddspd pwr serial eeprom power supply scl i serial bus clock sda i/o serial bus data line sa0 - sa2 i slave address select nc nc not connected
data sheet 9 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration table 4 pin configuration frontside backside pin# symbol pin# symbol pin# symbol pin# symbol 1 v ref 48 a0 93 v ss 140 nc / dm8/dqs17 2 dq0 49 nc / cb2 94 dq4 141 a10 3 v ss 50 v ss 95 dq5 142 nc / cb6 4 dq1 51 nc / cb3 96 v ddqd 143 v ddqd 5 dqs0 52 ba1 97 dm0/dqs9 144 nc / cb7 6dq2 key 98 dq6 key 7 v dd 99 dq7 8 dq3 53 dq32 100 v ss 145 v ss 9nc 54 v ddq 101 nc 146 dq36 10 nc 55 dq33 102 nc 147 dq37 11 v ss 56 dqs4 103 nc 148 v dd 12 dq8 57 dq34 104 v ddq 149 dm4/dqs13 13 dq9 58 v ss 105 dq12 150 dq38 14 dqs1 59 ba0 106 dq13 151 dq39 15 v ddq 60 dq35 107 dm1/dqs10 152 v ss 16 ck1 61 dq40 108 v dd 153 dq44 17 ck1 62 v ddq 109 dq14 154 ras 18 v ss 63 we 110 dq15 155 dq45 19 dq10 64 dq41 111 cke1 156 v ddq 20 dq11 65 cas 112 v ddq 157 s0 21 cke0 66 v ss 113 nc (ba2) 158 s1 22 v ddq 67 dqs5 114 dq20 159 dm5/dqs14 23 dq16 68 dq42 115 nc / a12 160 v ss 24 dq17 69 dq43 116 v ss 161 dq46 25 dqs2 70 v dd 117 dq21 162 dq47 26 v ss 71 nc 118 a11 163 nc 27 a9 72 dq48 119 dm2/dqs11 164 v ddq 28 dq18 73 dq49 120 v dd 165 dq52 29 a7 74 v ss 121 dq22 166 dq53 30 v ddq 75 ck2 122 a8 167 nc (a13) 31 dq19 76 ck2 123 dq23 168 v dd 32 a5 77 v ddq 124 v ss 169 dm6/dqs15 33 dq24 78 dqs6 125 a6 170 dq54 34 v ss 79 dq50 126 dq28 171 dq55 35 dq25 80 dq51 127 dq29 172 v ddq 36 dqs3 81 v ss 128 v ddq 173 nc 37 a4 82 v ddid 129 dm3/dqs12 174 dq60 38 v dd 83 dq56 130 a3 175 dq61 39 dq26 84 dq57 131 dq30 176 v ss
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration data sheet 10 v1.0, 2003-07 note: pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are nc (?not connected?) on 64 organised non-ecc modules. 40 dq27 85 v dd 132 v ss 177 dm7/dqs16 41 a2 86 dqs7 133 dq31 178 dq62 42 v ss 87 dq58 134 nc / cb4 179 dq63 43 a1 88 dq59 135 nc / cb5 180 v ddq 44 nc / cb0 89 v ss 136 v ddq 181 sa0 45 nc / cb1 90 nc 137 ck0 182 sa1 46 v dd 91 sda 138 ck0 183 sa2 47 nc / dqs8 92 scl 139 v ss 184 v ddspd table 5 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 128mb 16m 64 1 16m 1 6 4 13/2/10 8k 64 ms 7.8 s 256mb 32m 64 1 32m 8 8 13/2/11 8k 64 ms 7.8 s 256mb 32m 72 1 32m 8 9 13/2/11 8k 64 ms 7.8 s 512mb 64m 64 2 32m 8 16 13/2/11 8k 64 ms 7.8 s 512mb 64m 72 2 32m 8 18 13/2/11 8k 64 ms 7.8 s table 4 pin configuration (cont?d) frontside backside pin# symbol pin# symbol pin# symbol pin# symbol
data sheet 11 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration dq8 dq9 dq10 dq11 ldm i/o 0 i/o 1 i/o 2 i/o 3 d0 dq12 dq13 dq14 dq15 i/o 4 i/o 5 i/o 6 i/o 7 udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq24 dq25 dq26 dq27 ldqs i/o 0 i/o 1 i/o 2 i/o 3 d1 dq28 dq29 dq30 dq31 i/o 4 i/o 5 i/o 6 i/o 7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d3 dq60 dq61 dq62 dq63 i/o 4 i/o 5 i/o 6 i/o 7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d2 dq44 dq45 dq46 dq47 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq32 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dm1/dqs10 s 0 s s s s ldqs dqs1 dm0/dqs9 dqs0 dm3/dqs12 dqs3 dm2/dqs11 dqs2 dm5/dqs14 dqs5 dm4/dqs13 dqs4 dm6/dqs15 dqs6 dm7/dqs16 dqs7 udqs ldm udm udqs ldm udm ldqs udqs a0 - a13 a0-a13: sdrams d0 - d3 ba0 - ba1 ba0-ba1: sdrams d0 - d3 a0 serial pd a1 a2 sa0 sa1 sa2 sda scl ras ras : sdrams d0 - d3 cas cas : sdrams d0 - d3 cke0 cke: sdrams d0 - d3 we we : sdrams d0 - d3 udm udqs ldm ldqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 nc 2 sdrams 2 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d3 v dd /v ddq d0 - d3 d0 - d3 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be main- tained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 7.5 ohms 5% wp spd v dd spd figure 1 block diagram - one rank 16m 64 ddr sdram dimm hys64d16301gu using 16 organized sdrams
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration data sheet 12 v1.0, 2003-07 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 d0 dm0/dqs9 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d7 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 s 0 s s s s s s s s ba0 - ba1 ba0-ba1: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 scl dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 2 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5% 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 v ref v ddid strap: see note 4 wp spd v dd spd dq4 i/o 3 i/o 4 figure 2 block diagram - one rank 32m 64 ddr-i sdram dimm hys64d32 00gu / hys64d32300eu using 8 organized sdrams
data sheet 13 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d9 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 s 0 s 1 s s s s s s s s s s s s s s s s cke1 cke: sdrams d8 - d15 ba0 - ba1 ba0-ba1: sdrams d0 - d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 4 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% scl wp spd v dd spd figure 3 block diagram - two rank 64m 64 ddr-i sdram dimm hys64d64 20gu using 8 organized sdrams
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration data sheet 14 v1.0, 2003-07 figure 4 block diagram - one rank 32m 72 ddr-i sdram dimm hys72d32 00gu using 8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d8 s 0 s s s s s s s s ba0 - ba1 ba0-ba1: sdrams d0 - d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 i/o 4 i/o 5 i/o 6 i/o 7 s dqs8 dm8/dqs17 dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 3 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. bax, ax, ras , cas , we resistors: 5.1 ohm + 5% scl wp spd v dd spd
data sheet 15 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d10 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d17 ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d17 s 0 s 1 s s s s s s s s s s s s s s s s * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 6 sdrams 6 sdrams 6 sdrams cke1 cke: sdrams d9 - d17 * wire per clock loading ba0 - ba1 ba0-ba1: sdrams d0 - d17 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 dm d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s s dqs8 dm8/dqs17 dqs dqs table/wiring diagrams dqs dqs dqs dqs dqs dqs dqs dqs dqs v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref *ck2/ck2 v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp spd v dd spd figure 5 block diagram - two rank 64m 72 ddr-i sdram dimm hys72d64 20gu using 8 organized sdrams
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules pin configuration data sheet 16 v1.0, 2003-07 figure 6 clock net wiring 6 dram loads r = 120 ? 5% dimm connector dram1 dram2 dram3 dram4 dram5 dram6 4 dram loads r = 120 ? 5% dimm connector dram1 dram2 cap. cap. dram5 dram6 3 dram loads r = 120 ? 5% dimm connector dram1 cap. dram3 cap. dram5 cap. 2 dram loads r = 120 ? 5% dimm connector dram1 cap. cap. cap. dram5 cap. 1 dram loads r = 120 ? 5% dimm connector cap. cap. dram3 cap. cap. cap. ck ck cap. = 1/2 ddr sdram input capacitance; 1.0 pf 20%
data sheet 17 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 6 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma? table 7 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v f ck 166 mhz 4) input reference voltage v ref v ddq / 2 ? 50 mv v ddq / 2 v ddq / 2 + 50 mv v f ck >166mhz 2)4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ? 0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ? 0.3 v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6)
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics data sheet 18 v1.0, 2003-07 vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7) input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 8) output high current, normal strength driver i oh ??16.2ma v out = 1.95 v 8) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 8) 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between the input level on ck and the input level on ck . 7) the ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per ddr sdram component table 7 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/test condition 1) min. typ. max.
data sheet 19 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics 3.2 current conditions and specification table 8 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , distributed refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics data sheet 20 v1.0, 2003-07 table 9 i dd specification (pc2700, ?6) part number & organization hys64d16301hu-6-c hys64d32000hu-6-c hys72d32000hu-6-c hys64d64020hu-6-c hys72d64020hu-6-c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?6 ?6 ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. typ. max. typ. max. i dd0 260 300 480 600 540 675 736 904 828 1017 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 320 380 560 680 630 765 816 984 918 1107 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 14 18 28 36 31.5 40.5 56 72 63 81 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 100 340 200 240 225 270 400 480 450 540 ma 5) i dd2q 68 96 136 192 153 216 272 384 306 432 ma 5) i dd3p 44 60 88 120 99 135 176 240 198 270 ma 5) i dd3n 136 160 256 304 288 342 512 608 576 684 ma 5) i dd4r 340 400 560 680 630 765 816 984 918 1107 ma 3)4) i dd4w 360 440 600 720 675 810 856 1024 963 1152 ma 3) i dd5 540 640 1080 1280 1215 1440 1336 1584 1503 1782 ma 3) i dd6 5.6 11.2 11.2 22.4 12.6 25.2 44.8 22.4 25.2 25.2 ma 5) i dd7 820 960 1440 1720 1620 1935 1696 2024 1908 2277 ma 3)4)
data sheet 21 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics table 10 i dd specification (pc3200, ?5) part number & organization hys64d16301hu-5-c hys64d32000hu-5-c hys72d32000hu-5-c hys64d64020hu-5-c hys72d64020hu-5-c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. typ. max. typ. max. i dd0 280 340 560 640 630 720 848 984 954 1107 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 340 420 640 760 720 855 928 1104 1044 1242 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 14 18 28 36 31.5 40.5 56 72 63 81 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 120 144 240 288 270 324 480 576 540 648 ma 5) i dd2q 76 104 152 208 171 234 304 416 342 468 ma 5) i dd3p 48 64 96 128 108 144 192 256 216 288 ma 5) i dd3n 152 184 288 344 324 387 576 688 648 774 ma 5) i dd4r 400 480 680 800 765 900 968 1144 1089 1287 ma 3)4) i dd4w 420 520 720 840 810 945 1008 1184 1134 1332 ma 3) i dd5 600 720 1200 1440 1350 1620 1488 1784 1674 2007 ma 3) i dd6 6 11.6 12 23.2 13.5 26.1 24 46.4 27 52.2 ma 5) i dd7 900 1060 1600 1920 1800 2160 1888 2264 2124 2547 ma 3)4)
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics data sheet 22 v1.0, 2003-07 3.3 ac characteristics table 11 ac timing - absolute specifications ?6/?5 parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.5 +0.5 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 6 12 5 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.45?0.4?ns 2)3)4)5) dq and dm input setup time t ds 0.45?0.4?ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? tbd ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? tbd ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) ? +0.45 ? +0.40 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) ? +0.55 ? +0.50 ns tsopii 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.75 ? 0.6 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 0.7 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.75 ? 0.6 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 0.7 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5)
data sheet 23 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules electrical characteristics read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 42 70e+3 40 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 60 ? 55 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 72 ? 65 ? ns 2)3)4)5) active to read or write delay t rcd 18 ? 15 ? ns 2)3)4)5) precharge command period t rp 18 ? 15 ? ns 2)3)4)5) active to autoprecharge delay t rap 18 ? 15 ? ns 2)3)4)5) active bank a to active bank b command t rrd 12 ? 10 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal t ck 2)3)4)5)11) internal write to read command delay t wtr 1?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8?7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 11 ac timing - absolute specifications ?6/?5 (cont?d) parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max.
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules spd contents data sheet 24 v1.0, 2003-07 4 spd contents table 12 spd codes for pc2700 modules ??6? part number & organization hys64d16301hu?6?c hys64d32300hu?6?c hys72d32300hu?6?c hys64d64320hu?6?c hys72d64320hu?6?c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2ranks 2ranks ?6 ?6 ?6 ?6 ?6 byte# description hex hex hex hex hex 0 programmed spd bytes in e2prom 128 80 80 80 80 80 1 total number of bytes in e2prom 256 08 08 08 08 08 2 memory type ddr-i = 07h ddr sdram 07 07 07 07 07 3 # of row addresses 13 0d 0d 0d 0d 0d 4 # number of column addresses 9/10 09 0a 0a 0a 0a 5 # of dimm banks 1/2 01 01 01 02 02 6 data width (lsb) 64/ 72 40 40 48 40 48 7 data width (msb) 0 00 00 00 00 00 8 interface voltage levels sstl_2.5 04 04 04 04 04 9 tck @ clmax (byte 18) [ns] 6 ns 60 60 60 60 60 10 tac sdram @ clmax (byte 18) [ns] 0.75 ns 70 70 70 70 70 11 dimm configuration type (non- / ecc) non-ecc/ecc 00000200 02 12 refresh rate self-refresh 7.8 s82828282 82 13 primary sdram width 16 / 8 10080808 08 14 error checking sdram width na / 8 00000800 08 15 tccd [cycles] t ccd =1 clk 01010101 01 16 burst length supported 2, 4 & 8 0e 0e 0e 0e 0e 17 number of banks on sdram 4 04040404 04 18 cas latency cas latency = 2 & 2.5 0c 0c 0c 0c 0c 19 cs latency cs latency = 0 01 01 01 01 01 20 we (write) latency write latency = 1 02 02 02 02 02 21 dimm attributes unbuffered 20 20 20 20 20
data sheet 25 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules spd contents 22 component attributes ? c1 c1 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 7.5ns 75757575 75 24 tac sdram @ clmax -0.5 [ns] 0.70 ns 70 70 70 70 70 25 tck @ clmax -1 (byte 18) [ns] not supported 00 00 00 00 00 26 tac sdram @ clmax -1 [ns] not supported 00 00 00 00 00 27 trpmin (ns) 18 ns 48 48 48 48 48 28 trrdmin [ns] 12 ns 30 30 30 30 30 29 trcdmin [ns] 18 ns 48 48 48 48 48 30 trasmin [ns] 42 ns 2a 2a 2a 2a 2a 31 module density per bank 128 mbyte/ 256 mbyte 20 40 40 40 40 32 tas, tcs [ns] 0.75 ns 75 75 75 75 75 33 tah, tch [ns] 0.75 ns 75 75 75 75 75 34 tds [ns] 0.45 ns 45 45 45 45 45 35 tdh [ns] 0.45 ns 45 45 45 45 45 36 to 40 not used ? 00 00 00 00 00 41 trcmin [ns] 60 ns 3c 3c 3c 3c 3c 42 trfcmin [ns] 72 ns 48 48 48 48 48 43 tckmax [ns] 12 ns 30 30 30 30 30 44 tdqsqmax [ns] 0.45 ns 2d 2d 2d 2d 2d 45 tqhsmax [ns] 0.55 ns 55 55 55 55 55 46 to 61 not used ? 00 00 00 00 00 62 spd revision revision 0.0 00 00 00 00 00 63 checksum of byte 0-62 (lsb only) ?e801130214 64 jedec id code for infineon ? c1 c1 c1 c1 c1 65 to 71 jedec id code for infineon ? 00 00 00 00 00 table 12 spd codes for pc2700 modules ??6? (cont?d) part number & organization hys64d16301hu?6?c hys64d32300hu?6?c hys72d32300hu?6?c hys64d64320hu?6?c hys72d64320hu?6?c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2ranks 2ranks ?6 ?6 ?6 ?6 ?6 byte# description hex hex hex hex hex
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules spd contents data sheet 26 v1.0, 2003-07 72 module manufacturer location ?xxxxxxxxxx 73 part number, char 1 ? 36 36 37 36 37 74 part number, char 2 ? 34 34 32 34 32 75 part number, char 3 ? 44 44 44 44 44 76 part number, char 4 ? 31 33 33 36 36 77 part number, char 5 ? 36 32 32 34 34 78 part number, char 6 ? 33 33 33 33 33 79 part number, char 7 ? 30 30 30 32 32 80 part number, char 8 ? 31 30 30 30 30 81 part number, char 9 ? 48 48 48 48 48 82 part number, char 10 ? 55 55 55 55 55 83 part number, char 11 ? 36 36 36 36 36 84 part number, char 12 ? 43 43 43 43 43 85 part number, char 13 ? 20 20 20 20 20 86 part number, char 14 ? 20 20 20 20 20 87 part number, char 15 ? 20 20 20 20 20 88 part number, char 16 ? 20 20 20 20 20 89 part number, char 17 ? 20 20 20 20 20 90 part number, char 18 ? 20 20 20 20 20 91 module revision code ? xx xx xx xx xx 92 test program revision code ?xxxxxxxxxx 93 module manufacturing date year ?xxxxxxxxxx 94 module manufacturing date week ?xxxxxxxxxx 95 to 98 module serial number ? xx xx xx xx xx 99 to 127 not used ? 00 00 00 00 00 table 12 spd codes for pc2700 modules ??6? (cont?d) part number & organization hys64d16301hu?6?c hys64d32300hu?6?c hys72d32300hu?6?c hys64d64320hu?6?c hys72d64320hu?6?c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2ranks 2ranks ?6 ?6 ?6 ?6 ?6 byte# description hex hex hex hex hex
data sheet 27 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules spd contents table 13 spd codes for pc3200 modules ??5? part number & organization hys64d16301hu?5?c hys64d32300hu?5?c hys72d32300hu?5?c hys64d64320hu?5?c hys72d64320hu?5?c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2ranks 2ranks ?5 ?5 ?5 ?5 ?5 byte# description hex hex hex hex hex 0 programmed spd bytes in e2prom 128 80 80 80 80 80 1 total number of bytes in e2prom 256 08 08 08 08 08 2 memory type ddr-i = 07h ddr sdram 07 07 07 07 07 3 # of row addresses 13 0d 0d 0d 0d 0d 4 # number of column addresses 9/10 09 0a 0a 0a 0a 5 # of dimm banks 1/2 01 01 01 02 02 6 data width (lsb) 64/ 72 40 40 48 40 48 7 data width (msb) 0 00 00 00 00 00 8 interface voltage levels sstl_2.5 04 04 04 04 04 9 tck @ clmax (byte 18) [ns] 5 ns 50 50 50 50 50 10 tac sdram @ clmax (byte 18) [ns] 0.50 ns 50 50 50 50 50 11 dimm configuration type (non- / ecc) non- ecc/ecc 00 00 02 00 02 12 refresh rate self-refresh 7.8 s 82 82 82 82 82 13 primary sdram width 16 / 8 10080808 08 14 error checking sdram width na / 8 00000800 08 15 tccd [cycles] t ccd =1 clk01010101 01 16 burst length supported 2, 4 & 8 0e 0e 0e 0e 0e 17 number of banks on sdram 4 04 04 04 04 04 18 cas latency cas latency = 2, 2.5, 3 1c 1c 1c 1c 1c 19 cs latency cs latency = 0 01 01 01 01 01 20 we (write) latency write latency = 1 02 02 02 02 02 21 dimm attributes unbuffered 20 20 20 20 20 22 component attributes ? c1 c1 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 6.0 ns 60 60 60 60 60
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules spd contents data sheet 28 v1.0, 2003-07 24 tac sdram @ clmax -0.5 [ns] 0.50 ns 50 50 50 50 50 25 tck @ clmax -1 (byte 18) [ns] 7.5 ns 75 75 75 75 75 26 tac sdram @ clmax -1 [ns] 0.50 ns 50 50 50 50 50 27 trpmin (ns) 15 ns 3c 3c 3c 3c 3c 28 trrdmin [ns] 10 ns 28 28 28 28 28 29 trcdmin [ns] 15 ns 3c 3c 3c 3c 3c 30 trasmin [ns] 40 ns 28 28 28 28 28 31 module density per bank 128 mbyte/ 256 mbyte 20 40 40 40 40 32 tas, tcs [ns] 0.60 ns 60 60 60 60 60 33 tah, tch [ns] 0.60 ns 60 60 60 60 60 34 tds [ns] 0.40 ns 40 40 40 40 40 35 tdh [ns] 0.40 ns 40 40 40 40 40 36 to 40 not used ? 00 00 00 00 00 41 trcmin [ns] 55 ns 37 37 37 37 37 42 trfcmin [ns] 65 ns 41 41 41 41 41 43 tckmax [ns] 10 ns 28 28 28 28 28 44 tdqsqmax [ns] 0.40 ns 28 28 28 28 28 45 tqhsmax [ns] 0.50 ns 50 50 50 50 50 46 to 61 not used ? 00 00 00 00 00 62 spd revision revision 0.0 00 00 00 00 00 63 checksum of byte 0-62 (lsb only) ? e4 fd 0f fe 10 64 jedec id code for infineon ? c1 c1 c1 c1 c1 65 to 71 jedec id code for infineon ? 00 00 00 00 00 72 module manufacturer location ? xx xx xx xx xx 73 part number, char 1 ? 36 36 37 36 37 74 part number, char 2 ? 34 34 32 34 32 75 part number, char 3 ? 44 44 44 44 44 76 part number, char 4 ? 31 33 33 36 36 77 part number, char 5 ? 36 32 32 34 34 table 13 spd codes for pc3200 modules ??5? (cont?d) part number & organization hys64d16301hu?5?c hys64d32300hu?5?c hys72d32300hu?5?c hys64d64320hu?5?c hys72d64320hu?5?c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2ranks 2ranks ?5 ?5 ?5 ?5 ?5 byte# description hex hex hex hex hex
data sheet 29 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules spd contents 78 part number, char 6 ? 33 33 33 33 33 79 part number, char 7 ? 30 30 30 32 32 80 part number, char 8 ? 31 30 30 30 30 81 part number, char 9 ? 48 48 48 48 48 82 part number, char 10 ? 55 55 55 55 55 83 part number, char 11 ? 35 35 35 35 35 84 part number, char 12 ? 43 43 43 43 43 85 part number, char 13 ? 20 20 20 20 20 86 part number, char 14 ? 20 20 20 20 20 87 part number, char 15 ? 20 20 20 20 20 88 part number, char 16 ? 20 20 20 20 20 89 part number, char 17 ? 20 20 20 20 20 90 part number, char 18 ? 20 20 20 20 20 91 module revision code ? xx xx xx xx xx 92 test program revision code ? xx xx xx xx xx 93 module manufacturing date year ? xx xx xx xx xx 94 module manufacturing date week ? xx xx xx xx xx 95 to 98 module serial number ? xx xx xx xx xx 99 to 127not used ? 0000 0 table 13 spd codes for pc3200 modules ??5? (cont?d) part number & organization hys64d16301hu?5?c hys64d32300hu?5?c hys72d32300hu?5?c hys64d64320hu?5?c hys72d64320hu?5?c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2ranks 2ranks ?5 ?5 ?5 ?5 ?5 byte# description hex hex hex hex hex
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules package outlines data sheet 30 v1.0, 2003-07 a 4 0.1 a 0.1 bc 2.7 max. 133.35 b 0.15 a c 0.1 2.36 1 95 64.77 ?0.1 ac b = 1.27 x 120.65 2.175 6.62 6.35 49.53 92 3 min. 93 0.1 0.1 1.8 b ac 17.8 184 1.27 1 0.05 0.1 b a c detail of contacts 0.2 2.5 0.2 c 0.1 1.27 0.4 b 0.13 31.75 128.95 10 3.8 0.13 1) burr max. 0.4 allowed 1) on ecc modules only 5 package outlines figure 7 package outlines - raw card c (128 mbyte, 1 rank module) l-dim-184-18
data sheet 31 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules package outlines figure 8 package outline - raw card a (256 mbyte, 1 rank module, ?5 and ?6, ecc) l - dim -184-30 1 92 0.13 1 0.05 1.27 0.1 b a c detail of contacts 0.2 3 min. 3.8 93 2.5 0.2 1.8 0.1 c a 0.1 b 17.8 184 10 4 0.1 0.1 ac b 128.95 a 133.35 2.7 max. 0.15 b a c 6.35 0.1 2.36 1 64.77 ?0.1 c a b 1.27 x 95 120.65 = 2.175 6.62 49.53 92 b 0.13 31.75 1.27 c 0.1 0.4 1) burr max. 0.4 allowed 1) on ecc modules only
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules package outlines data sheet 32 v1.0, 2003-07 93 184 1 133.35 92 6.62 2.36 0.1 ?0.1 b a c 2.175 6.35 64.77 49.53 95 x 1.27 = 120.65 128.95 0.15 ac b a 0.13 31.75 0.1 4 0.1 ac b 0.1 a b c 0.1 1.8 3 min. 10 17.8 0.1 1.27 0.4 4 max. c detail of contacts 0.2 0.05 1 0.2 2.5 1.27 0.1 ac b 0.13 3.8 b 1) 1) 1) on ecc modules only burr max. 0.4 allowed figure 9 package outline - raw card b (512 mbyte, 2 rank module, ?5 and ?6, ecc) l - dim - 184 - 31
data sheet 33 v1.0, 2003-07 hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules package outlines figure 10 package outline - raw card a (256 mbyte, 1 rank module, ?5 and ?6, non ecc) l-dim-184-32 92 1 1.27 1 0.05 0.1 b a c detail of contacts 0.2 3 min. 2.5 0.2 3.8 93 0.13 0.1 1.8 a 0.1 c b 17.8 10 184 92 1.27 0.1 c 0.4 b 31.75 0.13 2.7 max. 6.62 0.1 1 2.36 64.77 95 x c b a ?0.1 6.35 120.65 1.27 = 2.175 49.53 92 0.1 4 0.1 a bc 128.95 133.35 b 0.15 a c a burr max. 0.4 allowed
hys[64/72]d[16x01/32x00/64x20]hu-[5/6]-c unbuffered ddr sdram modules package outlines data sheet 34 v1.0, 2003-07 4 c b 0.1 a 0.1 2.36 1 0.1 c 64.77 ?0.1 a b 95 133.35 128.95 1.27 x= 2.175 6.62 120.65 a 6.35 1.27 0.15 4 max. 49.53 92 0.4 31.75 b 0.13 c b 0.1 a c 0.1 detail of contacts 0.2 1.27 3.8 0.13 3 min. 93 0.2 2.5 1 0.05 0.1 ac b 1.8 0.1 b a c 184 10 17.8 burr max. 0.4 allowed figure 11 package outline - raw card b (512 mbyte, 2 rank module, ?5 and ?6, non ecc) l-dim-184-33
published by infineon technologies ag www.infineon.com

▲Up To Search▲

Price & Availability of HYS64D32300HU-6-C

	To Download HYS64D32300HU-6-C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .